Packaged semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include one or more semiconductor dies mounted on a substrate and encased in a plastic protective covering or covered by a heat-conducting lid. The die can include active circuits (e.g., providing functional features such as memory cells, processor circuits, and/or imager devices) and/or passive circuits (e.g., capacitors, resistors, etc.) as well as bond pads electrically connected to the circuits. The bond pads can be electrically connected to terminals outside the protective covering to allow the die to be connected to higher level circuitry.
To provide additional functionality, additional semiconductor dies can be added to a semiconductor device assembly. One approach to including additional semiconductor dies involves stacking the dies over the substrate. To facilitate the electrical connection of dies to the substrate, the dies can be arranged in a shingled stack, where each die is offset horizontally from a die below to leave exposed contact pads of the die that can be bonded (e.g., with a wirebond) to a corresponding bondfinger on the substrate. A drawback of this shingled stacking approach is the limit on the number of dies that can be stacked in this fashion, due to the increasing amount of overhang of each additional die added to the stack.
To address this limitation, shingled stacks of dies can include multiple groups of dies arranged in a shingled fashion, and offset either in the same direction (e.g., as shown in FIG. 1) or in opposing directions (as shown in FIG. 2). In this regard, FIG. 1 illustrates a semiconductor device assembly 100 in which a shingled stack 110 of dies on a substrate 101 includes two groups 102 and 103 of dies 104 which are shingled in the same offset direction, and electrically connected to bondfingers 120 on the substrate 101 by wirebonds 121. As can be seen with reference to FIG. 1, the wirebonds 121 of the first group 102 of dies 104 are underneath an overhang region 111 of the second group 103, and therefore must be formed before the second group 103 of dies 104 is stacked over the first group 102. Moreover, the bottommost die 104 of the second group 103 must be spaced above the topmost die 104 of the first group 102 by a sufficient distance (e.g., provided by a thicker layer of die attach material 105) to allow for a wirebond 121 thereto. Accordingly, drawbacks of this arrangement include the multiple stacking and wirebonding operations that must be iteratively performed, as well as the different die attach material thicknesses, at an increase in manufacturing cost and complexity.
Similar challenges are presented in forming the semiconductor device assembly illustrated in FIG. 2, in which the groups of dies are shingled with opposing offset directions. In this regard, FIG. 2 illustrates a semiconductor device assembly 200 in which a shingled stack 210 of dies on a substrate 201 includes two groups 202 and 203 of dies 204 which are shingled in opposing offset directions, and electrically connected to bondfingers 220 on the substrate 201 by wirebonds 221. As can be seen with reference to FIG. 2, at least some of the wirebonds 221 of the first group 202 of dies 204 are underneath an overhang region 211 of the second group 203, and therefore must be formed before the second group 203 of dies 204 is stacked over the first group 202. Accordingly, drawbacks of this arrangement include the multiple stacking and wirebonding operations that must be iteratively performed, as well as the provision of additional bondfingers in the substrate, at an increase in manufacturing cost and complexity.